1. Field of the Invention
The invention relates to communication networks. More specifically, the invention relates to processing bit streams.
2. Description of the Related Art
A digital transmission line that uses wire-pair and coaxial cable is known as a T-carrier. T-carriers include T1 and T3 lines. A T1 line is a point to point digital communications circuit that carries 24 64 kbits/s channels (“Digital Hierarchy-Formats Specification”, American National Standards for Telecommunications, ANSI T1.107, 1995). The bits on the T1 circuit are sent as frames. Each frame consists of 24 8 bit channels resulting in 192 bits per frame (“Digital Hierarchy-Formats Specification”, American National Standards for Telecommunications, ANSI T1. 107, 1995). The frames are sent at a rate of 8,000 frames per second (“Digital Hierarchy-Formats Specification”, American National Standards for Telecommunications, ANSI T1 0.107, 1995). This transfer rate provides an aggregate payload data rate of approximately 1.544 Mbits/s (“Digital Hierarchy-Formats Specification”, American National Standards for Telecommunications, ANSI T1.107, 1995). A framing bit for synchronization increases the size of each frame to 193 bits. The framing bit cycles through a framing bit pattern. A receiver searches for this framing bit pattern to achieve synchronization of the bit stream it is receiving. This bit format is referred to as digital signal level 1 (DS1).
A T-3 line is a digital transmission circuit that supports 28 T1 lines. The bit rate for a T1 line is approximately 44.736 Mbits/s. The bit format of the bit streams carried over T3 lines is referred to as digital signal level 3 (DS3). DS1 signals are multiplexed into DS3 signals. The multiplexing process is a 2 step process (“The Fundamentals of DS3”, 1992). Four DS1 signals are bit by bit interleaved to form a DS2 signal. Seven DS2 signals are multiplexed to form a DS3 signal.
FIG. 1 (Prior Art) is a diagram of a DSn deframer. A DS3 bit stream 101 and a clock signal 103 enter a line interface unit 105. The line interface unit 105 feeds the bit stream 101, clock signal 103, and a valid bit stream 107 into a DS3 deframer 102. The DS3 deframer 102 sync hunts the bit stream received from the line interface unit 105. Each of the seven DS2 subchannels (a signal bit stream 113 and subchannel bit stream 115) carried in the DS3 signal 101 is fed into individual DS2 deframers 106. Individual clocks are generated for each DS2 deframer with the DS2 clock rate. From each of the DS2 deframers 106, a bit stream 117 and a subchannel bit stream 119 is fed into four DS1 deframers 110, for a total of twenty-eight DS1 deframers 110. A clock for each of these DS1 deframers is generated with a DS1 clock rate. Hence, a total of 36 clocks (1 DS3 clock+7 DS2 clocks+28 DS1 clocks) are generated to deframe a single DS3 bit stream. A deframed bit stream 121 is sent to a destination external to the DSn deframer from each of the DS1 deframers 110.
Deframing more than one DS3 bit stream requires a network element with a 1:1 relationship of DSn deframers to DS3 bit streams. Alternatively, a DSn deframer with a 1:n relationship to DS3 bit streams becomes increasingly complicated and costly since the number of deframers and clocks increase linearly with the number of DS3 bit streams to be processed.